face

Blaise GENEST

CNRS Researcher (CR1)
in Computer Science at
IRISA in Team SUMO
Campus de Beaulieu
F-35042 Rennes Cedex
            France
Phone: +33 (0)2 99 84 73 49
Fax:     +33 (0)2 99 84 71 71
email: bgenest@irisaXXXREMOVEXXX.fr
formerly associated with IPAL (2010-2012)
UMI CNRS (Unité Mixte Internationale)
Institute for Infocomm Research (I2R)
1 Fusionopolis Way
#21-01 Connexis (South Tower)
      Singapore 138632

 

 

 

 

 

 

I was also Adjunct Associate Professor at School of Computing, National University of Singapore (NUS) (2011-2013).

  • My resume in En | Fr

  • Research interests:

    Model Checking: Automata and Verification, Distributed Systems, Games Theory.
    Stochastic Systems: BioInformatics (Metabolic Pathways), Complex Systems.
    Misc: Data Bases, Pattern Matching, Hardware Architecture.

  • Publications

    ( some words about rankings )


  • Habilitation Manuscript


  • PhD Students:

    Matthieu Pichené (2014-)
    Bruno Karelovic (2012-)
    former student: Debmalya Biswas (2006-2009)


  • Projects

    STOCH-MC
    (Primary Inverstigator)
    ANR-13-BS02-0011-01.
    ANR

    AVERTS
    Indo-French CEFIPRA



    DISTOL
    INRIA Associated Team



  • Former projects:

    PEPS INSIS (CNRS) Projet AABS (Primary Investigator).

    Projet ActivDoc Funded by CREATE, Region Bretagne (WorkPackage Leader).

    ANR-06-MDCA-005 DOCFLOW, (WorkPackage Leader).

    Associated Team DST Funded by INRIA

    ANR-06-SETI-xxx DOTS

  • I was Elected Member of the Comité National de la Recherche Scientifique, section 07 (now section 06 and 07) and CID 43 (now CID 51), 2008-2012

    ( I am not serving there anymore, but the new websites are website of the section 06 and website of the section 07 )


  • Teaching/Enseignement

    Advanced Techniques of Verification (10h, Lecture, Master 2 in Rennes, 2015-2016)
    Models of Concurrency (5h, Lecture, Master 2 in Rennes,2006-2007).
    Verification (4h, Lecture, 4th year in Warwick,2005).
    Programming in Java (42h, TP, DEUG 1,2003-2004).
    Hardware Architecture (36h, TD, IUP 1, 2003-2004).